This invention relates to programmable devices that include specialized multiplier blocks that can be configured as finite impulse response (FIR) filters, and more particularly to such programmable devices in which the specialized multiplier blocks may be interconnected to create larger filters, including multi-channel filters.
As programmable devices (such as, e.g., programmable logic devices, or PLDs) have become larger, it has become more common to add dedicated blocks to perform particular functions that have become more common in programmable devices. For example, at some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as sum-of-products logic, otherwise known as product term or P-TERM logic); such embedded blocks might even be provided in different sizes on the same device. Other types of memory, such as read-only memory (ROM) or shift registers, also have been provided. More recently, multiplier circuits have been provided on programmable devices. Whereas in prior programmable devices space was not available for dedicated multipliers, current larger devices can accommodate multipliers. This spares users from having to create multipliers by configuring the available logic. Moreover, as described in commonly-assigned U.S. Pat. No. 6,538,470, which is hereby incorporated by reference in its entirety, specialized multiplier blocks may be provided including multipliers and other arithmetic circuits such as adders and/or subtracters and/or accumulators. Such blocks are sometimes referred to as “multiplier-accumulator blocks” or “MAC blocks.” Such blocks, for example, may be useful in digital signal processing, such as is performed in audio applications, and therefore such specialized multiplier blocks also are sometimes referred to as “DSP blocks.”
One use for such specialized multiplier blocks is in filtering operations. In particular, one such specialized multiplier block described in commonly-assigned U.S. Pat. No. 6,556,044, can be configured as either a Direct Form I FIR filter or as a Direct Form II FIR filter. As seen there, in a Direct Form I FIR filter, several multiplier outputs are added using an adder chain, which also provides for chaining to the adder chain of another specialized multiplier block to create longer Direct Form I FIR filters. Indeed, a Direct Form I FIR filter of any length (up to the limit imposed by the number of specialized multiplier blocks on the programmable device) can be created.
On the other hand, as also seen there, a Direct Form II FIR filter uses an adder tree rather than an adder chain. Creating longer filters would require an adder tree outside the specialized multiplier blocks to add the results from plural specialized multiplier blocks. Because it is not known in advance how many blocks a user may want to add together, and because such adder trees consume large device areas, it is not practical to provide such adder trees on a programmable device. As a result, users who want to construct long Direct Form II FIR filters must use soft logic of the programmable device to construct the required adder tree. While this allows creation of an adder tree of any size, soft logic adders are slower, and consume a large amount of device resources.
It would be desirable to be able to provide a specialized multiplier block on a programmable device that allows large Direct Form II FIR filters to be constructed